1. Field of Invention
The present invention relates to integrated circuit design for semiconductor memory and more specifically a control gate decoder for dual gate memory cells and specifically a twin MONOS EEPROM.
2. Description of Related Art
Both Flash and MONOS EEPROM are comprised of an array of cells that can be independently programmed and read. Select transistors can be added to the array to cut the capacitance on lines, and can be used to enable cells to be erased. Metal Oxide Semiconductor (MOS) field effect transistors are the individual memory units of both types of EEPROMS. The Flash MOS transistor includes a source, drain, and floating gate with a control gate connected to a Word Line (WL). Various voltages are applied to the word line to program the cell with a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, or to erase the cell.
In the conventional MONOS MOS transistor the programmable component under the control gate in the MONOS device is a nitride layer as shown in FIG. 1, which is a cross section of a twin MONOS array. The twin MONOS memory unit is comprised of a control gate CG with a left and right component, CG_L and CG_R, under which two separate sites, ML and MR, are used as storage sites in the composite nitride layers. The bit line diffusion, BL, lies under the control gate, CC, and an independent polysilicon word line, WL, lies between the control gates of adjacent cells. The array scheme U.S. Pat. No. 6,011,725 (Eitan) is directed toward a polysilicon word line routed above the control gates of the cells connected to the word line WL. A twin MONOS memory structure is referenced in U.S. Pat. No. 6,248,633, (Ogura, et al.). Various voltages applied to the control gate CG in combination with bit line BL and word line WL voltages, are used to program the left and right cell components with a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. The separate word line polysilicon provides additional control that enables the operation of the control gates.
U.S. Pat. No. 6,248,633 (Ogura et al) is directed toward a twin MONOS cell structure having an ultra short control gate channel with ballistic electron injection into the nitride storage sites and fast low voltage programming. U.S. patent application Ser. No. 10/099,030 dated Mar. 15, 2002 is directed toward providing a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability in a MONOS memory cell. U.S. patent application Ser. No. 09/810,122 dated Mar. 19, 2001 is directed toward an array architecture of nonvolatile memory and its operation methods using a metal bit diffusion array.
EEPROM memory cells in an array of rows and columns may be connected in various configurations such as NAND or NOR, both of which require different decode strategies for the control gate and word lines. In a NAND arrangement, the cells in a column are connected in series with the source of one cell connected to the drain of the cell in the next row. Control gates (for MONOS EEPROM) are connected across columns in a row along with word line so that all cells in a word line row must be selected. The word line decoder supplies one word line with a select voltage, while applying an override voltage to all other unselected word lines within a block.
Another type of decoder is used in conjunction with a NOR type memory configuration, where the control gates of the cells in a row are connected. The drains of the cells in a column are connected to a bit lines, and the sources of the cells in one row are connected together. In this typical NOR arrangement, a decoder would select one row by selecting a word line while all other word lines are unselected.
It is an objective of the present invention to provide a control gate line decoder for a twin MONOS EEPROM memory array.
It is also an objective of the present invention to provide a control gate line decoder which allows for one or more bit selection within a word line during read and program operations.
It is also another objective of the present invention to provide a control gate line decoder for a two bit erase.
It is still another objective of the present invention to provide a control gate line decoder for a block erase.
It is yet another objective of the present invention to provide a control gate line decoder for incorporating the voltage selection requirements of a dual bit memory array.
It is still yet another objective of the present invention to provide a control gate line decoder that can override voltages on left and right neighboring control gates.
In a higher density dual bit type array, such as a twin MONOS memory array shown in FIG. 1, one bit line of a cell is shared between two storage sites called xe2x80x9chard bitsxe2x80x9d. A selected memory cell requires specific voltage conditions not only on the bit line of the selected cell, but also on the bit line of the neighbor cell. The bit line of the neighbor cell is adjacent to the selected storage site of the selected cell. Therefore, if the left hard bit of a cell is selected, then the neighbor cell is to the left, and if the right hard bit of a cell is selected then the neighbor cell is to the right.
During a single hard-bit operation, one bit line provides the source voltage while an adjacent bit line provides the drain voltage. The dual bit type array is similar to the NOR type configuration where all bit line diffusions passing under a word line are separately connected to an individual bit line, but differs from the NOR in that all diffusions in a column are connected to a respective bit line. In a matrix configuration, the word line is connected to all the word line polysilicon segments in a row, and is thereby the mechanism through which one row array is selected. However, each control gate of a cell is separate from the word line of a row, connecting columns through control gate lines (CG) running perpendicular to the word lines and parallel to the bit lines. This allows selection of specific control gate lines within a row of memory cells.
The control gate selection is similar to bit line selection in a NOR type matrix configuration with the requirement of neighbor cell bit line voltages in addition to the selected cell voltages during single hard-bit operation. If one out of Y cells are selected during a particular mode, then one out of Y control gate lines will hold the selected voltage VCGs, while the control gates of corresponding neighbor cells can be applied with an override voltage VCGo. The selected word line determines the row selected, but the control gate lines determine the columns in that row that are selected. In providing the correct voltages on the control gate lines, a decoder specifically designed for control gate lines needs to be connected to the memory matrix.
Under both read and program operating conditions, a MONOS Memory requires the application of a particular override voltage to the control gates adjacent to the control gates of the selected cell. If the left storage site of a cell is selected to be read, or programmed, the neighboring control gate to the left of the storage site requires an override voltage, and similarly if the right storage site is selected, the neighboring control gate on the right requires the override voltage.
An override voltage used during a read operation blocks the effects of a neighboring adjacent cell on the cell selected to be read. During a program operation and an erase operation, the override voltage is used on neighboring cells to block the effects of the selected cell on the unselected neighboring cell. For a read operation an override voltage is applied to the control gate of an adjacent cell, which is greater than the control gate voltage of the selected cell, preventing the adjacent cell from affecting the read operation of the selected cell. For a program operation an override voltage is applied to the control gate of an adjacent cell, which is lower than the control gate voltage of the selected cell, preventing the adjacent cell from being selected.
There are various schemes for selecting the left or right storage sites for read and program operations. In FIG. 2A the left side of Cell[x] is selected and one strategy would be to simply apply the control gate override voltage to only the immediate neighbor of the selected cell. Bit line voltages on neighbor cells may be the same since a left/right override selection is through the control gates. A second scheme shown in FIG. 2B is to apply the same override voltages on both the left and right neighbor of the selected cell, and differentiating the position of the override cell through the BL voltages. Both these strategies are possible using the decoding scheme proposed herein.
Simultaneous erase of the left and right components of a twin MONOS memory unit requires a negative voltage applied to the respective control gate, and a positive voltage on the corresponding bit line. Unselected control gates may be held at 0V, with no consideration for an override voltage.
During read or program, the decoder provides override voltages on both left and right control gates of neighbor cells, or just on the control gate immediately adjacent to the selected control gate component. The control gate decoder supplies any unselected cell (not including override cells) with an unselected voltage, typically 0V. The control gate decode unit associated with an individual control gate line, is comprised of two blocks of pass transistors.
Depending on the voltage selection and timing requirements, the blocks of a decode unit may be implemented as a single high voltage transistor or a complementary transmission gate. One block passes the high voltages using a PMOS transistor as the main component using the high control gate voltage at the source and the control gate line connected to the respective memory cell as the drain. The high control gate voltages passed by the decode block are the selected and override control gate voltages used during read or program and the unselected cell voltages during erase.
The second block of the decode unit passes the low voltages to the control gate line, with an NMOS transistor as the fundamental component using the low control gate voltage for a source bias and the control gate line for the drain connection. Both blocks share an input signal YCG provided by logic circuits, which switch the control gate line between the high and low voltages. The control gate decoder is in itself, an array of decode units that parallels the memory array, with one decode unit for each control gate line. A group of control gate decoders has individual YCG input signals so that corresponding control gate lines may be selectively connected to the correct voltages. Even decode units belonging to even control gate lines all have high voltage lines connected to a single VCGHIEV line. Similarly, odd decode units belonging to odd control gate lines all have high voltage lines connected to a single VCGHIOD line. Thus a cell, whether even or odd, can have the selected control gate high voltage at the same time that the neighbor cell sees a different high voltage for overriding a control gate. In the control gate decode scheme of the present invention, all the low voltage lines from the decode units are connected to a single VCGLO line without respect to even or odd cells. The low voltages for the twin MONOS memory of the present invention are applied to all unselected cells during read or program and to selected cells during erase mode.